News

Feb 20, 2025

Compact inverse designed vertical coupler with bottom reflector for sub-decibel fiber-to-chip coupling on silicon on insulator platform | Scientific Reports

Scientific Reports volume 15, Article number: 2925 (2025) Cite this article 456 Accesses Metrics details Inverse design via topology optimization has led to innovations in integrated photonics and

Scientific Reports volume 15, Article number: 2925 (2025) Cite this article

456 Accesses

Metrics details

Inverse design via topology optimization has led to innovations in integrated photonics and offers a promising way for designing high-efficiency on-chip couplers with a minimal footprint. In this work, we exploit topology optimization to design a compact vertical coupler incorporating a bottom reflector, which achieves sub-decibel coupling efficiency on the 220-nm silicon-on-insulator platform. The final design of the vertical coupler yields a predicted coupling efficiency of −0.35 dB at the wavelength of 1550 nm with a footprint of 14 µm \(\times\) 14 µm, which is considerably smaller than conventional grating couplers. Its topology-optimized geometry can be realized by applying one full-etch and one 70-nm shallow-etch process and the fabricability is also guaranteed by a minimum feature size around 150 nm. Analysis of the potential fabrication imperfections indicates that the topology-optimized coupler is more resilient to in-plane variations, as the deviation of approximately ±100 nm in the misalignment of the topology-optimized features, ±20 nm in the size of the topology-optimized features, and ±10 nm in shallow etch depth yields an additional 1-dB loss as a penalty at the wavelength of 1550 nm. The proposed vertical coupler can further miniaturize photonic integrated circuits and enable highly-efficient networks between optical fibers and other photonic devices.

Photonic integrated circuits have been a promising platform for practical implementation in various fields, especially for emerging quantum technologies such as quantum key distribution1,2,3,4,5,6,7, quantum communication8,9 and photonic quantum computing10,11,12,13,14, due to their scalability and mechanical and thermal stability. Since the monolithic integration of the essential building blocks of a photonic quantum system, namely single photon sources, photonic components that process quantum information and single-photon detectors, is still technically challenging, on-chip couplers, particularly the ones with sub-decibel coupling efficiency in telecom C band, are pivotal in interfacing the integrated quantum photonic circuits and optical fibers. They enable efficient networks to other photonic integrated systems or off-chip devices without losing a great amount of single photons.

On-chip couplers can be generally divided into two categories: in-plane couplers15,16,17 and out-of-plane couplers18,19,20,21,22,23,24,25,26,27. Compared to in-plane couplers like edge couplers, out-of-plane couplers or grating couplers offer relatively high alignment tolerance, enable wafer-scale inspection or testing and can be placed flexibly on the chip, easing the complexity of the circuit design. They neither require special treatment, e.g. cleaving and polishing processes, at the edge of the chip to create a quality facet, which lowers the difficulty in chip fabrication. Despite the advantages mentioned above, conventional grating couplers usually require a non-zero fiber coupling angle to mitigate the loss caused by the back reflection from the second-order diffraction28. Such a coupling scheme is not only disadvantageous in alignment routines but also introduces difficulties and additional costs to the packaging of the photonic integrated circuits. Although conventional grating couplers using the vertical coupling scheme, where the fiber coupling angle is zero, have been demonstrated29,30,31,32, they usually require a long tapered waveguide, typically in the length of 40 \(\upmu\)m to 200 \(\upmu\)m, to reduce the loss during mode conversion into the waveguide fundamental mode. Such a characteristic inevitably hinders the miniaturization of photonic integrated circuits for high-density integration and scalability.

(a) Schematic illustrating the working principle and functionality of the topology-optimized vertical coupler. (b) Perspective view (omitting the top oxide layer) and (c) the cross-section of the objects in the three-dimensional FDTD simulations carried out during the topology optimization (not to scale). The size of the design region (yellow area) is 14 µm \(\times\) 14 µm \(\times\) 70 nm. The dimensions of the strip waveguide are 450 nm \(\times\) 220 nm on top of a 2-µm buried oxide layer (cyan area below the silicon device layer). A layer of perfect electric conductor (PEC) is placed below the buried oxide layer and serves as a bottom reflector (blue area).

In this context, inverse design via topology optimization becomes a favorable method as it promises compact integrated components with comparable or even better performance compared to the traditional counterparts. Generally, this technique varies the spatial distribution of the refractive index to optimize the user-defined figure-of-merit (FoM) functions that relate to the device performance. Specific requirements, such as central operating wavelength, thickness of the cladding and device layers, etc., can also be considered in advance to simplify the entire design workflow. Numerous novel designs of photonic integrated components, such as wavelength-dependent demultiplexers33,34, power splitters34,35, spatial mode multiplexers34,36 and grating couplers37,38,39,40, have been investigated or experimentally demonstrated on a variety of material platforms like diamond and lithium niobate. Among these platforms, silicon-on-insulator (SOI) is an attractive one for scalable implementation since it leverages the mature complementary metal-oxide semiconductor (CMOS) manufacturing technologies. Topology-optimized SOI couplers using the vertical coupling scheme have also been simulated and experimentally demonstrated 38,39,40. Despite their compact footprint, however, the designs presented in Refs. 38,39,40 exhibit a relatively high simulated coupling loss of \(-3.0\) dB, \(-1.9\) dB and \(-1.1\) dB at the wavelength of 1550 nm, respectively. This issue presumably arises from the high substrate leakage38,39 or the strong back reflection due to the fully-etched grating geometry40. To facilitate ultrahigh-efficiency vertical fiber-to-chip coupling with a minimal spatial footprint, a new design that can address the aforementioned issue is imperative.

In this work, we apply the topology optimization to inversely design a 14 \(\upmu\)m \(\times\) 14 \(\upmu\)m vertical coupler which has a shallow-etched geometry on the 220-nm SOI platform (Fig. 1(a)). The topology-optimized vertical coupler incorporates a bottom reflector to improve the diffraction directionality. The simulated coupling efficiency of the acquired design is \(-0.35\) dB (92.2%) at 1550 nm and also has a flat spectral response within the telecom C band. Compared to the conventional vertical grating couplers in Refs.29,31 with the state-of-the-art coupling efficiency of \(-0.6\) dB and \(-0.75\) dB in simulations, respectively, our design is predicted to have improved performance with a significantly reduced spatial footprint. Further details of the aforementioned SOI vertical couplers can be found in the comparison shown in Table 1. We anticipate our new design will further extend the applications of the topology-optimized couplers in various photonic applications and chip networks requiring high-efficiency vertical fiber-to-chip coupling.

We exploit the inverse design tool, Lumopt, together with the finite-difference time-domain (FDTD) solver (Ansys Lumerical FDTD) to perform the topology optimization and design the vertical coupler. In a three-dimensional FDTD simulation environment, a design region with dimensions of 14 \(\upmu\)m \(\times\) 14 \(\upmu\)m (Fig. 1b) is set up to fully capture the incoming light from a standard single-mode optical fiber (e.g. SMF-28 with a mode field diameter of \(\approx\) 10.4 \(\upmu\)m at 1550 nm) and to obtain the maximal attainable coupling efficiency. Furthermore, a perfect electric conductor (PEC) layer is inserted underneath a 2-µm buried oxide layer (Fig. 1c) and functions as a metal bottom reflector to enhance the directionality of the coupler. Details of the settings regarding the simulation and topology optimization are illustrated in Methods.

The topology optimization starts with ”bulk initial condition”, i.e. initially the design region is full of silicon (iteration 1 in Fig. 2a). At the beginning of the optimization, the distribution of the reflective index varies in a greyscale fashion and first becomes like focusing periodic gratings (iteration 10 in Fig. 2a). Following multiple iterations, it is transformed into slender hollows and islands (iteration 100 in Fig. 2a). The device performance also grows quickly to −2 dB within 10 iterations (Fig. 2b). To achieve a good balance between the device performance and the computation time of the whole optimization process, the maximum number of iterations in the greyscale phase is set to 60. After reaching this limit, the optimization enters the phase of material binarization where the material in each pixel in the design region gradually becomes either silicon or SiO\(_2\) (referred to the grey dashed line in Fig. 2b). The device performance increases further but later drops slightly. It eventually converges at \(-0.35\) dB (92.2%). The total iteration number of the optimization is 247 and the duration of the optimization is approximately 10 days using a desktop equipped with Intel i9-13900K and DDR5 random-access memory. After the optimization is completed, the final structure is simulated with the FDTD method subsequently with a broader wavelength range and higher spectral resolution, namely from 1500 nm to 1600 nm with an increment of 1 nm, to ensure the acquired vertical coupler performs decently in the desired bandwidth. The simulated coupling efficiency of the vertical coupler shows a flat response within the telecom C band (solid orange line in Fig. 2c). At the wavelength of 1550 nm, the coupling efficiency is consistently \(-0.35\) dB with a 3-dB bandwidth \(\Delta _{\mathrm {3\,dB}}\) of 35 nm. Particularly, the bottom reflector recycles the direct transmission towards the substrate and thus considerably enhances the coupling efficiency. The importance of the bottom reflector can also be stressed by the notable increase in the substrate leakage upon the exclusion of the reflector (grey line in Fig. S1 in Supporting Information).

Afterward, the structure of the coupler is extracted, converted into chip layout files of standard format (the graphic data stream file in this case) and imported into the three-dimensional FDTD simulation environment. We then repeat the FDTD simulation to ensure the integrity of the coupler’s performance after the extraction. The simulation result shows that the performance of the topology-optimized vertical coupler remains almost unaffected, as the spectral response shifts to the right marginally (dashed orange lines in Fig. 2c). In addition, since the directionality of an out-of-plane coupler is usually sensitive to the distance between the silicon device layer and the silicon substrate, we sweep the thickness of the buried oxide (BOX) layer to ensure it is optimal for constructive reflection towards the coupler structure (Fig. 2d). Due to the phenomenon of wave interference, the coupling efficiency of the coupler at 1550 nm is periodic (having a period of \(\approx\) 520 nm) with respect to the BOX thickness. Besides, the coupling efficiency is maximized when BOX thickness is 2 µm, which is a predetermined parameter in the optimization. This indicates that, given a certain BOX thickness, structures that facilitate constructive interference after the light is reflected by the bottom reflector are explored during the topology optimization. Also, we investigate the alignment tolerance of the acquired vertical coupler along x and y directions (solid and dashed lines in Fig. 2e, respectively). Only the coupling efficiency with respect to the offset along the y-axis is symmetric due to the x-axis symmetry of the acquired design (referred to the result of iteration 247 in Fig. 2a and the rendered image in Fig. 4a). The lateral alignment error resulting in an additional 3-dB loss \(\sigma _{\mathrm {3\,dB}}\) is around ±3.5 µm from the center of the coupler along the x and y axes. In this sense, common alignment routines with, for instance, piezo positioning stages should be applicable to this topology-optimized vertical coupler.

(a) The snapshots of the topology-optimized structure in iterations 1, 10 100, 200 and 247. The refractive index of the material in the design region is presented in a gradient color scheme, where the maroon (white) color corresponds to the reflective index of silicon (SiO\(_2\)) and the colors in between represent that of the pseudo mixture of the two materials. (b) Evolution of the coupling efficiency at the wavelength of 1550 nm during the optimization. (c) Simulated coupling efficiency of the topology-optimized vertical coupler with respect to the wavelength before (solid line) and after extraction (dashed line). The 3-dB bandwidth \(\Delta _{\textrm{3dB}} \approx\) 35 nm. (d) Coupling efficiency of the acquired topology-optimized vertical coupler at 1550 nm versus the thickness of the BOX layer. The dashed line indicates the coupling efficiency when the BOX thickness is 2 µm. (e) Coupling efficiency of the acquired topology-optimized vertical coupler at 1550 nm versus the position offset along the x (solid line) and y (dashed line) axes. The alignment error giving rise to an additional 3-dB loss \(\sigma _{\mathrm {3\,dB}}\) is around ±3.5 µm along the x and y axes from the center of the coupler.

Finally, we investigate the tolerance of the coupler to the fabrication imperfections in chip production. This includes the influence of the fabrication deviation \(\delta\) in the depth of shallow etching, size of the topology-optimized geometry, and the alignment of optical mask on the spectral response of the coupling efficiency. First of all, the deviation from the nominal shallow etch depth \(d_\mathrm{{etch}} = 70\) nm in a range of \(\delta = \pm 50\) nm leads to noticeable changes in the device performance (Fig. 3a). The spectral response of the coupling efficiency exhibits a large blue (red) shift when \(\delta > 0\) (\(\delta < 0\)) and the position of the peak coupling efficiency falls outside of the spectral range we investigate when \(\delta =\) \(\pm 50\) nm (upper plot in Fig. 3a). The simulation results also indicate that the deviation in the etch depth \(\delta \approx \pm 10\) nm gives rise to an additional 1-dB loss to the coupling efficiency at the operating wavelength of 1550 nm (lower plot in Fig. 3a). Next, we resize the individual shapes that compose the topology-optimized structure to mimic the fabrication error in the size of fine features (Fig. 3b). With a spectral shift of around \(\pm 30\) nm, the peak coupling efficiency decreases to around \(-1.43\) dB when \(\delta = \pm 50\) nm (upper plot in Fig. 3b). Besides, the spectral response becomes more irregular when the shape size becomes smaller (i.e. \(\delta < 0\)). The coupling efficiency at 1550 nm obtains a 1-dB penalty when \(\delta \approx +20\) nm and \(\delta \approx -25\) nm (lower plot in Fig. 3b). Lastly, we emulate the mask misalignment by introducing a displacement in a range of \(\delta = \pm 100\) nm along the x (Fig. 3c) and y axes (Fig. 3d) individually to the designed structure. For the misalignment along the x axis, the peak coupling efficiency drops to \(-1.32\) dB and \(-1.53\) dB when \(\delta = +100\) nm and \(-100\) nm, respectively, accompanied by a spectral shift of approximately \(\pm 5\) nm (upper plot in Fig. 3c). In the case of y-axis misalignment, due to the x-axis symmetry of the topology-optimized structure, displacement along ± y directions by the same magnitude is equivalent and the spectral responses thus overlap (upper plot in Fig. 3d). The peak coupling efficiency declines to \(-1.41\) dB when \(\delta = \pm 100\) nm and the spectral response of the y-axis misalignment shifts less than that of x misalignment. The 1-dB penalty appears when \(\delta \approx \pm 90\) nm and \(\delta \approx \pm 100\) nm for x and y misalignment, respectively (lower plot in Fig. 3c, d). In general, the reduction in overall efficiency and spectral shift are less prominent when the deviation is in the size of the topology-optimized structure and mask misalignment compared to that in the etch depth, which suggests that the hole-based topology-optimized coupler is more resilient to the in-plane fabrication imperfections, especially the misalignment, and more sensitive to the depth deviation of the shallow etching.

Investigation on the influence of the fabrication deviations on the device performance. The deviations include (a) etch depth (with nominal etch depth \(d_\mathrm{{etch}} = 70\) nm), (b) size of the topology-optimized structure, and optical mask misalignment along the (c) x and (d) y axes. The upper plots show the spectral responses of the coupling efficiency with various fabrication deviations \(\delta\), whereas the lower plots display the coupling efficiency at the wavelength of 1550 nm as a function of fabrication \(\delta\). The dashed grey line indicates the position of an additional 1-dB penalty (i.e. \(-1.35\) dB).

The optimization at the end leads to a ”hole-based” structure as the algorithm seemingly focuses on forming hollows on the bulk silicon to diffract and couple the light into the strip waveguide efficiently (Fig. 4a). Overall, the final design contains slender hollows and islands and nearly circular or elliptical holes. The width of the long chains of islands and hollows and the diameter of the holes are roughly equal to or larger than 150 nm, which fits the constraint we preset on the minimum feature size in the optimization. One can vaguely observe certain periodic patterns in the whole structure. Such patterns are assumed capable of modulating the grating diffraction mode to improve the mode matching condition with the target Gaussian mode profile, akin to the conventional grating structure engineering methods like randomization18 or apodization19 of the grating period.

(a) Three-dimensional rendered image of the final design of the vertical coupler. The hollows in the rendered images should be filled with the cladding material, SiO\(_2\), which is omitted in the image. (b) Simulated y-component of the electric field \(E_y(x,y)\) at the wavelength of 1550 nm overlapped with the geometry of the topology-optimized vertical coupler. The input light in the simulation is y-polarized. (c) Left panel: forward (blue) and backward (green) transmission, upward reflection (red) and substrate leakage (grey) with respect to the wavelength. The solid and dashed lines specify the optical responses of the designs acquired in two scenarios, namely (i) the optimization including the bottom reflector and (ii) reintroducing the bottom reflector after the optimization without the bottom reflector, respectively. Right panel: schematic for the forward and backward transmission, upward reflection and substrate leakage.

Besides, the resulting design features an arc-like geometry over the middle region as the hollows and islands are arranged into confocal chains (Fig. 4a). Similar to the focusing grating couplers20,41,42, such a geometry is in principle advantageous to adiabatically transform the input optical mode into the fundamental mode of the strip waveguide while the whole structure only occupies a relatively small area. This phenomenon can also be verified in the simulated distribution of the electric field component \(E_y(x,y)\) at the wavelength of 1550 nm (Fig. 4b). After the light is coupled into the vertical coupler from the top, its mode profile becomes concavely shaped and then is gradually transformed into the fundamental mode of the strip waveguide. In addition, the geometry near the bottom edge is assumed to function as a distributed Bragg reflector to redirect the light back to the strip waveguide, as the backward transmission of the structure is strongly suppressed within the range of 1540 nm to 1560 nm (solid green line in Fig. 4c). Despite the high coupling efficiency, the major loss, which is the upward reflection of \(\approx 4.3\%\) (solid red line in Fig. 4c), comes from the fact that there is still a certain amount of the light traveling through the topology-optimized structures after being reflected by the bottom reflector. Nevertheless, owing to the bottom reflector, the substrate leakage is drastically reduced and is thus nearly zero (solid grey lines in Fig. 4c). We also consider the scenario where the bottom reflector is excluded in the topology optimization and reintroduced after the final design is delivered (geometry of the resulting design and other details are shown in Fig. S2 in Supporting Information). However, we observe that the upward reflection increases within the range of 1530 nm to 1570 nm (dashed red line in Fig. 4c) after reinserting the bottom reflector underneath the 2-\(\upmu\)m BOX layer. This implies that the design generated in this manner is suboptimal for recoupling the reflected light within the preset wavelength range. Despite the comparable peak performance, this results in a narrower operating bandwidth compared to the original design (dashed and solid blue lines in Fig. 4c). Therefore, incorporating the bottom reflector into the topology optimization is critical for optimizing the device performance in the desired bandwidth.

It is also possible to have various designs of the topology-optimized vertical coupler by choosing other initial conditions to expand the component library. For instance, the topology optimization can begin with the ”mixture initial condition”, i.e. a pseudo material of which the refractive index is the average of silicon and SiO2 is in the discretized design region initially. This gives rise to an ”island-based” geometry (Fig. S3 (a) in Supporting Information), as the algorithm seemingly tends to transform the pseudo material into long silicon islands that can guide the light into the strip waveguide. According to our simulation results, both island- and hole-based topology-optimized vertical couplers have similar spectral responses and peak performances (Fig. S3 (b) in Supporting Information). One may then select a suitable design based on, for instance, the preference or the capability of a chip foundry. There are several possible ways to further improve the design and the performance of the topology-optimized coupler. For instance, the operating wavelength or the 3-dB bandwidth of the vertical coupler can be further expanded if a broader wavelength range in which the FoM function is maximized is used in the topology optimization. In this case, however, more wavelength points should be considered in the optimization to obtain a flat and usable response of the devices, which is more computationally expensive and may significantly increase the duration of the optimization. In addition, initial conditions with various predefined geometries, e.g. a focusing silicon grating structure with Bragg reflectors put close to the back edge, in the discretized design region could also be introduced to explore new designs of vertical on-chip couplers. Ultimately, one may modify the optimization algorithm that also parameterizes the depth of the design region to produce a topology-optimized structure that contains full-etched and shallow-etched hollows. Effectively, this type of topology-optimized coupler could behave like the interleaved43,44 or L-shaped grating couplers29,45 as the dual-etched slots strengthen the diffraction effect and improve the directionality of light propagation. In this way, the coupler could suppress the loss caused by the light that travels toward the silicon substrate even without a bottom reflector, which greatly reduces the cost and complexity of the fabrication.

In summary, we inversely design a compact vertical coupler on the 220-nm SOI platform via topology optimizations and provide an in-depth investigation of the outcome. The predicted coupling efficiency of the topology-optimized vertical coupler, which incorporates a bottom reflector, is \(-0.35\) dB at the wavelength of 1550 nm and the 3-dB bandwidth is 35 nm. As the area of the couplers is only 14 µm \(\times\) 14 µm, the footprint in a chip layout can be reduced considerably compared to conventional grating couplers. In addition, the dimensions of the sophisticated features in the design, such as the diameter of the small holes and the width of the long chains of slender islands and hollows, are in general equal to or greater than 150 nm, which ensures the fabricability on the SOI platform. The investigation on the fabrication imperfection indicates that a bearable 1-dB penalty occurs when the etch depth deviates by around ± 10 nm, the size of the topology-optimized features deviates by around \(\pm 25\) nm and mask alignment deviates by around \(\pm 100\) nm. This also suggests that the proposed topology-optimized coupler is more tolerant to the in-plane imperfections than the error in the etch depth. Altogether, we believe our study will facilitate practical applications of topology-optimized components, especially the couplers, further in various fields in integrated photonics.

We exploit the inverse design tool, Lumopt, together with the finite-difference time-domain (FDTD) solver (Ansys Lumerical FDTD) to perform the topology optimization. Specifically, the optimizer employed in the inverse design tool is based on the ”L-BFGS-B” method from SciPy package. In the topology optimization, a design region with a thickness of 70 nm is set up on top of a silicon layer that has a thickness of 150 nm (Fig.1a). Both the design region and the silicon layer are connected to a strip waveguide that has the dimensions of 450 nm \(\times\) 220 nm and the entire device is embedded in the SiO\(_2\) cladding material (Fig.1b). The space in the design region is discretized into pixels parameterized by \(\rho (x,y) \in [0, 1]\), where x and y denote the position of the pixel in the x and y directions. In each pixel, the permittivity of the material \(\epsilon\) is in the linear interpolation

and then adjusted iteratively to maximize user-defined FoM functions by solving the optimization problem. Eventually, the material in each pixel becomes either solid (silicon) or void (SiO\(_2\)) by applying the Heaviside function

for threshold projection, where \(\beta\) and \(\eta\) are the threshold parameters. In this material binarization phase, the permittivity of the material in each pixel, given by

becomes binary after ramping up \(\beta\) to form a physically-feasible structure.

The size of the design region is configured to be 14 µm \(\times\) 14 µm \(\times\) 70 nm. The 14-µm length and width are set up for a better accommodation of the Gaussian profile of the light from the single-mode fiber, considering a mean field diameter of an SMF-28 fiber of around 10.4 µm. The 70-nm thickness is planned for the creation of shallow-etched sub-wavelength topology-optimized structure that is able to diffract the light efficiently into the strip waveguide. The light source in the simulations is set to be a Gaussian source positioned at the center of the design region. Its polarization state is perpendicular to the strip silicon waveguide (i.e. y-polarized) and the mode field diameter is set to be 10.4 µm, mimicking the light emitted from an SMF 28 optical fiber. The incident angle of the Gaussian light source is also set to 0° to fulfill the vertical fiber-coupling scheme. A perfect electric conductor layer is then placed underneath a 2-µm buried oxide layer and serves as a metal bottom reflector to reflect the light that propagates through the coupler (Fig.1b) and let the coupler recouple the light into the waveguide. Such a reflector is commercially available and can be implemented by depositing the metal layer in the trenches etched on the backside of the wafer and beneath the couplers18 or using the benzocyclobutene (BCB) bonding method where the metal layer expands all over the wafer46,47.

To obtain a flat and continuous spectral response in the operating wavelength, a set of 5 wavelength points, from 1540 nm to 1560 nm with an increment of 5 nm, at which the FoM function is maximized is preset in the optimization. Since the final setup has a mirror symmetry along the x direction, the boundary conditions of the FDTD simulations is set to be anti-symmetric at the y-boundary in order to reduce the computation time by a factor of 2 in each FDTD simulation. Essentially, the FoM function in the topology optimization is defined as the overlap between the input mode in the strip waveguide and the fundamental mode of the strip waveguide, which indicates the efficiency of the light coupling into the waveguide fundamental mode. Finally, a constraint on the minimum feature size of the topology-optimized structure is set to 150 nm to guarantee the fabricability of the final structures.

During the topology optimization, three-dimensional FDTD simulations are initialized and carried out with the settings mentioned above. Such a single FDTD simulation in general requires around 30 minutes and the gradient of the FoM function in the parameter space is calculated based on the simulation results. Within the design region, the refractive index of the material in the pixels is then updated according to the gradient of the FoM function computed previously for the next iteration to maximize the FoM function. Owing to the adjoint method applied in the topology optimization48, in general, only two FDTD simulations, commonly named forward and adjoint simulations, are required to determine the gradient of the FoM function, which greatly improves the efficiency of the whole optimization. Still, since the adjoint method is a gradient-descent method, the initial condition of the design region may significantly influence the final output of the topology optimization.

Data generated during the current study are available from the corresponding author on reasonable request.

Sibson, P. et al. Chip-based quantum key distribution. Nat.Commun. 8, 13984 (2017).

Article ADS PubMed PubMed Central CAS Google Scholar

Bunandar, D. et al. Metropolitan quantum key distribution with silicon photonics. Phys. Rev. X 8, 021009 (2018).

CAS Google Scholar

Zhang, G. et al. An integrated silicon photonic chip platform for continuous-variable quantum key distribution. Nat. Photon. 13, 839–842 (2019).

Article ADS MATH CAS Google Scholar

Beutel, F., Gehring, H., Wolff, M. A., Schuck, C. & Pernice, W. Detector-integrated on-chip QKD receiver for GHZ clock rates. npj Quantum Inf. 7(40) (2021).

Zhu, C.-X. et al. Experimental quantum key distribution with integrated silicon photonics and electronics. Phys. Rev. Appl. 17, 064034 (2022).

Article ADS CAS Google Scholar

Beutel, F. et al. Fully integrated four-channel wavelength-division multiplexed QKD receiver. Optica 9, 1121–1130 (2022).

Article ADS CAS Google Scholar

Sax, R. et al. High-speed integrated QKD system. Photon. Res. 11, 1007–1014 (2023).

Article MATH CAS Google Scholar

Paraiso, T. K. et al. A photonic integrated quantum secure communication system. Nat. Photon. 15, 850–856 (2021).

Article ADS MATH Google Scholar

Trenti, A. et al. On-chip quantum communication devices. J. Lightwave Technol. 40, 7485–7497 (2022).

Article ADS MATH CAS Google Scholar

Qiang, X. et al. Large-scale silicon quantum photonics implementing arbitrary two-qubit processing. Nat. Photon. 12, 534–539 (2018).

Article ADS MATH CAS Google Scholar

Arrazola, J. M. et al. Quantum circuits with many photons on a programmable nanophotonic chip. Nature 591, 54–60 (2021).

Article ADS PubMed PubMed Central MATH CAS Google Scholar

Vigliar, C. et al. Error-protected qubits in a silicon photonic chip. Nat. Phys. 17, 1137–1143 (2021).

Article MATH CAS Google Scholar

Qiang, X. et al. Implementing graph-theoretic quantum algorithms on a silicon photonic quantum walk processor. Sci. Adv. 7, eabb8375 (2021).

Article ADS PubMed PubMed Central CAS Google Scholar

Chi, Y. et al. A programmable qudit-based quantum processor. Nat. Commun. 13, 1166 (2022).

Article ADS PubMed PubMed Central MATH CAS Google Scholar

Hatori, N. et al. A hybrid integrated light source on a silicon platform using a trident spot-size converter. J. Lightwave Technol. 32, 1329–1336 (2014).

Article ADS MATH CAS Google Scholar

He, A., Guo, X., Wang, K., Zhang, Y. & Su, Y. Low loss, large bandwidth fiber-chip edge couplers based on silicon-on-insulator platform. J. Lightwave Technol. 38, 4780–4786 (2020).

Article ADS MATH CAS Google Scholar

Mu, X., Wu, S., Cheng, L. & Fu, H. Edge couplers in silicon photonic integrated circuits: A review. Appl. Sci. 10, 1538 (2020).

Article MATH CAS Google Scholar

Zaoui, W. S. et al. Bridging the gap between optical fibers and silicon photonic integrated circuits. Opt. Exp. 22, 1277–1286 (2014).

Article MATH CAS Google Scholar

Marchetti, R. et al. High-efficiency grating-couplers: Demonstration of a new design strategy. Sci. Rep. 7, 16670 (2017).

Article ADS PubMed PubMed Central MATH Google Scholar

Hoppe, N. et al. Ultra-efficient silicon-on-insulator grating couplers with backside metal mirrors. IEEE J. Sel. Top. Quantum Electron. 26, 1–6 (2019).

Article MATH Google Scholar

Marchetti, R., Lacava, C., Carroll, L., Gradkowski, K. & Minzioni, P. Coupling strategies for silicon photonics integrated chips. Photon. Res. 7, 201–239 (2019).

Article CAS Google Scholar

Cheng, L., Mao, S., Li, Z., Han, Y. & Fu, H. Grating couplers on silicon photonics: Design principles, emerging trends and practical issues. Micromachines 11, 666 (2020).

Article PubMed PubMed Central Google Scholar

Benedikovic, D. et al. Subwavelength index engineered surface grating coupler with sub-decibel efficiency for 220-nm silicon-on-insulator waveguides. Opt. Exp. 23, 22628–22635 (2015).

Benedikovic, D. et al. Sub-decibel silicon grating couplers based on l-shaped waveguides and engineered subwavelength metamaterials. Opt. Exp. 27, 26239–26250 (2019).

Nambiar, S., Ranganath, P., Kallega, R. & Selvaraja, S. K. High efficiency dbr assisted grating chirp generators for silicon nitride fiber-chip coupling. Sci. Rep. 9, 18821 (2019).

Hong, J., Spring, A. M., Qiu, F. & Yokoyama, S. A high efficiency silicon nitride waveguide grating coupler with a multilayer bottom reflector. Sci. Rep. 9, 12988 (2019).

Lomonte, E., Stappers, M., Kramer, L., Pernice, W. H. & Lenzini, F. Scalable and efficient grating couplers on low-index photonic platforms enabled by cryogenic deep silicon etching. Sci. Rep. 14, 4256 (2024).

Taillaert, D. et al. Grating couplers for coupling between optical fibers and nanophotonic waveguides. Jpn. J. Appl. Phys. 45, 6071 (2006).

Article ADS MATH CAS Google Scholar

Watanabe, T., Ayata, M., Koch, U., Fedoryshyn, Y. & Leuthold, J. Perpendicular grating coupler based on a blazed antiback-reflection structure. J. Lightwave Technol. 35, 4663–4669 (2017).

Article ADS CAS Google Scholar

Zhang, Z. et al. High-efficiency apodized bidirectional grating coupler for perfectly vertical coupling. Opt. Lett. 44, 5081–5084 (2019).

Article ADS PubMed MATH CAS Google Scholar

Liu, J. et al. High-performance grating coupler array on silicon for a perfectly-vertically mounted multicore fiber. J. Lightwave Technol. 40, 5654–5659 (2022).

Article ADS MATH CAS Google Scholar

Xiong, B., Ma, W., Wang, W., Hu, X. & Chu, T. Compact vertical grating coupler with an achromatic in-plane metalens on a 220-nm silicon-on-insulator platform. Opt. Exp. 30, 36254–36264 (2022).

Article CAS Google Scholar

Vercruysse, D., Sapra, N. V., Su, L., Trivedi, R. & Vučković, J. Analytical level set fabrication constraints for inverse design. Sci. Rep. 9, 8999 (2019).

Article ADS PubMed PubMed Central Google Scholar

Piggott, A. Y. et al. Inverse-designed photonics for semiconductor foundries. ACS Photon. 7, 569–575 (2020).

Article MATH CAS Google Scholar

Hansen, S. E., Arregui, G., Babar, A. N., Christiansen, R. E. & Stobbe, S. Inverse design and characterization of compact, broadband, and low-loss chip-scale photonic power splitters. Mater. Quantum Technol. 4, 016201 (2024).

Article ADS CAS Google Scholar

Shang, C. et al. Inverse-designed lithium niobate nanophotonics. ACS Photon. 10, 1019–1026 (2023).

CAS Google Scholar

Dory, C. et al. Inverse-designed diamond photonics. Nat. Commun. 10, 3309 (2019).

Article ADS PubMed PubMed Central MATH Google Scholar

Hammond, A. M., Slaby, J. B., Probst, M. J. & Ralph, S. E. Multi-layer inverse design of vertical grating couplers for high-density, commercial foundry interconnects. Opt. Exp. 30, 31058–31072 (2022).

Pita Ruiz, J. L. et al. Ultracompact silicon-on-insulator couplers for multicore fibers. ACS Photon. 10, 953–958 (2022).

MATH Google Scholar

Wang, L. et al. Single-etched fiber-chip coupler with a metal mirror on a 220-nm silicon-on-insulator platform for perfectly vertical coupling. Opt. Lett. 49, 2974–2977 (2024).

Article ADS PubMed MATH CAS Google Scholar

Van Laere, F. et al. Compact focusing grating couplers for silicon-on-insulator integrated circuits. IEEE Photon. Technol. Lett. 19, 1919–1921 (2007).

Article ADS MATH Google Scholar

Wang, Y. et al. Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits. Opt. Exp. 22, 20652–20662 (2014).

Article MATH Google Scholar

Alonso-Ramos, C. et al. Fiber-chip grating coupler based on interleaved trenches with directionality exceeding 95%. Opt. Lett. 39, 5351–5354 (2014).

Article ADS PubMed MATH CAS Google Scholar

Benedikovic, D. et al. High-directionality fiber-chip grating coupler with interleaved trenches and subwavelength index-matching structure. Opt. Lett. 40, 4190–4193 (2015).

Article ADS PubMed MATH CAS Google Scholar

Benedikovic, D. et al. L-shaped fiber-chip grating couplers with high directionality and low reflectivity fabricated with deep-UV lithography. Opt. Lett. 42, 3439–3442 (2017).

Article ADS PubMed MATH CAS Google Scholar

Higuera-Rodriguez, A. et al. Realization of efficient metal grating couplers for membrane-based integrated photonics. Opt. Lett. 40, 2755–2757 (2015).

Article ADS PubMed MATH Google Scholar

Bleiker, S. J., Dubois, V., Schröder, S., Stemme, G. & Niklaus, F. Adhesive wafer bonding with ultra-thin intermediate polymer layers. Sens. Actuators A Phys. 260, 16–23 (2017).

Article ADS CAS Google Scholar

Lalau-Keraly, C. M., Bhargava, S., Miller, O. D. & Yablonovitch, E. Adjoint shape optimization applied to electromagnetic design. Opt. Exp. 21, 21693–21701 (2013).

Article Google Scholar

Download references

Open Access funding enabled and organized by Projekt DEAL. The research was funded by Bundesministerium für Bildung und Forschung (PhotonQ, SiSiQ), Carl-Zeiss-Stiftung, Competence Center Quantum Computing Baden-Württemberg (Project QORA) and Deutsche Forschungsgemeinschaft (431314977, GRK2642).

Institute for Functional Matter and Quantum Technologies, University of Stuttgart, 70569, Stuttgart, Germany

Shiang-Yu Huang & Stefanie Barz

Center for Integrated Quantum Science and Technology (IQST), University of Stuttgart, 70569, Stuttgart, Germany

Stefanie Barz

You can also search for this author in PubMed Google Scholar

You can also search for this author in PubMed Google Scholar

S.-Y.H. conceived the idea, conducted the numerical simulations and optimizations and prepared the first paper draft of the work. S.-Y.H. and S.B. jointly discussed the results, contributed critical thoughts and provided revisions to the manuscript.

Correspondence to Shiang-Yu Huang.

The authors declare no competing interests.

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.

Reprints and permissions

Huang, SY., Barz, S. Compact inverse designed vertical coupler with bottom reflector for sub-decibel fiber-to-chip coupling on silicon on insulator platform. Sci Rep 15, 2925 (2025). https://doi.org/10.1038/s41598-025-86161-1

Download citation

Received: 09 August 2024

Accepted: 08 January 2025

Published: 23 January 2025

DOI: https://doi.org/10.1038/s41598-025-86161-1

Anyone you share the following link with will be able to read this content:

Sorry, a shareable link is not currently available for this article.

Provided by the Springer Nature SharedIt content-sharing initiative